(1) Field of the Invention
The present invention relates to the field of microprocessors. More specifically, the present invention relates to register stacks in microprocessors.
(2) Description of Related Art
A register stack architecture allows multiple procedures to efficiently share a large register file, by stacking procedure call frames in registers. Registers may be used by procedures for holding intermediate results, address indexing, passing parameters between calling and called procedures such as subroutines, etc.
In most modern microprocessor architectures with "non-stacked register architectures" the overhead of saving and restoring registers on procedure calls and returns limits the performance of a microprocessor or computer system. Since the call/return patterns of typical applications exhibit high call/return frequencies with small amplitudes, the hysteresis of a stacked register file causes a significant reduction in the number of stores at procedure calls (register spills) and loads at procedure returns (register fills). As processor frequency is increasing (access to processor faster) and access time to random access memory (RAM) is decreasing, but not as much as processor frequency is increasing reducing the number of memory accesses performed by a program will result in performance improvement in most computer systems.
While register stacking removes the number of register spill/fill operations, programs with deep procedure call chains may exhaust available registers--procedure calls may cause register stack overflows, while returns may cause underflows. Traditional processor architectures define over/underflow traps that vector to software overflow/underflow handlers to spill or fill registers in order to make room in the register stack. However, these techniques may slow down execution of programs which may need to stop to allow the overflow/underflow handlers to do their job.
Consequently, it is desirable to provide an apparatus and a method that uses excess processor memory bandwidth to dynamically spill/fill registers from the stacked register file to a backing store in memory concurrently with program execution such that spilling or filling may operate in parallel with the processor's execution of instructions. In such an environment it is desirable to provide a way of "synchronizing" spilling and filling of registers with a processor's execution of instructions when a switch from a source to a target context is required to make possible a return to the same context and resume operation in the source context as if no context switch occurred. It is also desirable to provide a way of saving and restoring, in an efficient manner, the contents of stacked registers of the stacked register file upon interrupt and return from interrupt, respectively.